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Samson Nesaraj, A.
- Preparation and Characterization of Doped Ceria Nano Particles by Chemical Precipitation
Authors
1 Department of Chemistry, Karunya University, Coimbatore – 641 114, Tamil Nadu, IN
Source
Asian Journal of Research in Chemistry, Vol 4, No 9 (2011), Pagination: 1447-1452Abstract
In this present research work, chemical precipitation technique was employed to synthesize doped ceria nano particles. The precursor materials, such as, cerium nitrate hexahydrate (basic material) and sodium hydroxide (precipitator material) were used to prepare different compositions of phase pure doped ceria (Ce0.9Gd0.1O2-δ, Ce0.9Y0.1O2-δ, Ce0.8Gd0.2O2-δ and Ce0.8Y0.2O2-δ) with an intention to use in solid oxide fuel cells (SOFCs) as electrolytes. The physicochemical properties of the resultant oxides were characterized by XRD, FT-IR, particle size analysis and SEM. The XRD results revealed the formation of well-crystalline cubic fluorite structure in all the doped ceria powders after calcination at 750°C. The SEM observation showed an average grain size of about 50 - 100nm for the optimal doped ceria powder and particle size analysis gave a narrow distribution of particle size. These results suggest that doped ceria can further improve the use of SOFC at low temperatures.Keywords
Ceria, SOFC, Chemical Precipitation, Physical Characterization.- Flexible TFT Using Stacked Nano Zro2/Al2o3
Authors
Source
International Journal of Innovative Research and Development, Vol 2, No 5 (2013), Pagination:Abstract
The ever growing Semiconductor industry is turning today towards high-κ gate dielectrics in transistor manufacturing processes to meet the need for higher speed transistors while keeping power consumption under control. The thickness of silicon dioxide (SiO2) is very less so it produces the tunneling current leakage, high power consumption and produces high heat when scaling of the transistor. A technique has been developed to fabricate a Thin Film Transistors (TFT) using stacked high- κ nanomaterials. Here in this work using stacked ZrO2 and Al2O3 as high-κ dielectric nanomaterials, ITO/PET substrate which is flexible, and ZnO as a semiconducting layer provides high performance to the device. Through this proposed approach the above problems are solved and the transistor could be shrunk below 32 nm.